module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    wire mul1_out, mul2_out;
    assign mul1_out = E?w:Q;
    assign mul2_out = L?R:mul1_out;
    always @(posedge clk) begin
        Q <= mul2_out;
    end

endmodule